125 MHz MEMS oscillator with ±20 ppm stability
The DSC1502AI3A-125M0000: The ±20 ppm stability means the clock edge stays within 20 parts per million of 125 MHz over temperature and aging — tight enough for most serial data links, Ethernet PHY reference clocks, and FPGA transceiver PLLs that need a clean source without external trimming.
Supply voltage accepts 2.5V to 3.3V, covering both 2.5V FPGA banks and 3.3V logic rails without a separate regulator.
