Active production — MEMS-based 100 MHz clock source
HCSL output — PCIe and high-speed serial fit
HCSL (High-Speed Current Steering Logic) is the differential clock standard specified by PCIe Gen 1 through Gen 4 and is also common in Ethernet, FPGA reference clocks, and SerDes PLLs. The 100 MHz frequency aligns with the base reference for PCIe Gen 1/2/3 (100 MHz ±300 ppm), and the ±25 ppm stability of this part provides substantial margin against the 300 ppm total budget, leaving headroom for the PLL and board-level spread-spectrum if needed.
The 2.25V to 3.6V supply range covers 2.5V and 3.3V rails, so the same BOM line can serve both voltage domains without a separate regulator or level translator on the clock input.
6-SMD footprint — board layout notes
The 7.00 mm x 5.00 mm, 6-SMD no-lead package (0.90 mm seated height) is a standard form factor shared by many quartz oscillators, so the PCB footprint can often serve either a MEMS or a quartz device with a layout change. The no-lead construction means the terminations are flush with the package body—verify the solder-paste stencil aperture for a 0.50 mm pad width to avoid bridging between the signal and ground pads during reflow.