100 MHz MEMS XO with HCSL output — clock-tree fit note
The DSC1124NI1-100.0000T: Its HCSL output is a current-mode logic level commonly used in PCIe reference clocks and high-speed SERDES interfaces — the 42 mA max supply current reflects the drive strength needed to maintain the differential swing into a 50-Ω terminated line.
Supply voltage and power-down flexibility
The Enable/Disable function (pin-controlled) drops the supply current from 42 mA to 22 mA when the clock is gated, which helps reduce standby power in systems that cycle clock domains.
MEMS resonator vs quartz — phase-noise and reliability angle
For a 100 MHz reference, the integrated jitter in the 12 kHz–20 MHz band (not listed here) would be the deciding metric — the ±50 ppm stability covers the long-term accuracy, not the short-term phase noise.
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