100 MHz HCSL clock source for PCIe and SERDES reference
The DSC1124NE1-100.0000 is a 100 MHz HCSL (High-Speed Current Steering Logic) oscillator built on a MEMS resonator — a drop-in replacement for quartz-based XOs in PCIe Gen1/2/3 reference clock and SERDES applications where the 100 MHz frequency and HCSL output levels are required. HCSL is a differential, low-swing output standard that drives 50-ohm terminated lines directly, common on server motherboards, switch fabric, and FPGA clock trees. The MEMS base gives faster startup and better shock resistance than a quartz crystal — useful if the board sees vibration in transit or in a fan-cooled chassis.
Runs on any rail from 2.25V to 3.6V — covers 2.5V and 3.3V logic without an extra regulator. Frequency stability is ±50 ppm over the full temperature and voltage range — tight enough for a 100 MHz clock in a 1 GbE PHY or a PCIe reference, though a 25 ppm or 10 ppm part would be needed for a 10 GbE or SyncE application.
Enable/Disable function and current draw
That 20 mA saving matters on a power-limited board running multiple oscillators, but the disable current is still higher than a true power-down mode on some competitors.