100 MHz HCSL clock source for high-speed serial interfaces
The DSC1124CL1-100.0000: HCSL swings 700-900 mV peak-to-peak with a common-mode around 350 mV, so it drives a differential pair directly without the level translation a CMOS output would need. Start-up time is typically under 5 ms, compared to 10-20 ms for many quartz-based XOs.
Supply voltage and temperature envelope
This is a single-supply part — no separate core and I/O voltages to manage. At 105°C the frequency stability holds to ±50 ppm, so the part works in engine-bay or rooftop enclosures without active cooling. The disable current is still significant — for battery-powered designs that spend most of their time asleep, a load switch on the supply rail may be worth adding.
Package and board-fit for hand assembly
The Enable/Disable pin (pin 1 on the standard 6-pin footprint) lets you tri-state the output for boundary-scan testing or to save power when the downstream device is idle. When disabled, the output goes high-impedance, not a fixed logic level.