156.25 MHz fixed-frequency XO — the PCIe and 10GbE reference clock
The Microchip DSC1124CI2-156.2500 is a fixed-frequency XO (Standard) delivering 156.25 MHz with HCSL output, the differential clock standard for PCIe Gen1/2/3 reference and 10GbE SerDes PLLs. The HCSL swing (0.7V peak-to-peak into 50 ohms to GND) drives the clock tree directly without external translation — no AC-coupling caps needed at the receiver if the DC bias is handled by the termination.
Supply and output — single-rail HCSL
The Enable/Disable pin (pin 1 on the 6-SMD) tri-states the output when pulled low, drawing 22 mA max in disable mode vs 42 mA max when active. That is tight enough for 156.25 MHz in a PCIe Gen3 reference (requires ±300 ppm total) or a 10GbE MAC/PHY clock, but not Stratum 3 — if the design needs holdover or wander specs, a TCXO or OCXO is the next step up.
Lifecycle and sourcing — active, no EOL pressure
In the current allocation environment, 156.25 MHz MEMS oscillators have seen spot premiums on short-dated orders, but this part is not on a constrained fab node.