133.33 MHz HCSL clock source for high-speed interfaces
The DSC1124CI2-133.3300 is a MEMS-based XO (Standard) delivering a 133.33 MHz HCSL output — a common reference clock for PCIe Gen1/2/3, Ethernet PHYs, and FPGA transceivers that require a differential, low-jitter clock with a controlled swing. HCSL (High-Speed Current Steering Logic) swings 700-900 mV peak-to-peak into a 50-Ω termination to Vcc-2V, which means the output amplitude is set by the termination, not the supply — the same board layout works across the full 2.25V to 3.6V supply range.
±25 ppm stability over industrial temperature
The 6-VDFN package (3.20mm x 2.50mm, 0.90mm seated height) is a standard MEMS oscillator footprint, compatible with common quartz XO layouts — verify the pad pitch against your existing land pattern before committing.