HCSL output at 50 MHz — what it buys you
The DSC1124CE1-050.0000T: This is a 50 MHz XO with HCSL output — a differential, low-swing clock standard that drives 50-ohm terminated lines directly. The HCSL swing (typically 700-800 mV peak-to-peak) reduces EMI compared to a single-ended LVCMOS clock at the same frequency, and the differential pair rejects common-mode noise on the PCB trace. If your PCIe reference clock or SerDes PLL expects HCSL levels, this oscillator mates without a level translator. No external load capacitors, no startup margin calculation.
Supply flexibility and power gating
At 42 mA max supply current, the oscillator draws about 140 mW at 3.3 V — budget that into the rail's total load.
The 6-SMD No Lead package measures 3.20 mm x 2.50 mm with a seated height of 0.90 mm — a compact footprint that fits dense layouts. The no-lead construction means the terminations are flush with the package body; the PCB land pattern should match the manufacturer's recommended footprint for the 6-pad layout. Surface-mount reflow per JEDEC J-STD-020 is standard.