MEMS clock for 50 MHz HCSL lanes
The Microchip DSC1124CE1-050.0000 is a 50 MHz MEMS-based XO with HCSL output in the 3.2 mm × 2.5 mm 6-SMD no-lead package. HCSL (High-Speed Current Steering Logic) delivers a differential swing that drives PCIe reference clocks, SerDes reference lanes, and FPGA transceiver reference inputs directly — no external termination resistors to ground are needed beyond the standard 50 Ω pull-downs to VSS at each receiver pin.
This means the clock stays within ±50 ppm of 50 MHz regardless of where the board rail sits or how the ambient temperature drifts inside a ventilated enclosure — no additional supply regulation or temperature compensation is required at the oscillator socket. The disable current is still present because the MEMS resonator and PLL remain powered — the output buffer is tri-stated, not the core. For a power-down state that draws less than 22 mA, the supply rail to the oscillator must be gated externally.
Active production and order path
Sourced through authorized and independent distribution; pricing and lead time are confirmed at RFQ against the BOM quantity.