125 MHz HCSL reference for high-speed serial links
The DSC1124BE1-125.0000T is a MEMS-based XO delivering a 125 MHz HCSL output — the standard reference frequency and logic level for PCIe Gen1/2/3, SATA, and Ethernet SerDes clocking. The HCSL output swings differentially with a typical 0.7V peak-to-peak amplitude into a 50-ohm terminated line, matching the input requirements of most PCIe clock buffers and PLLs without external level translation. Its ±50 ppm frequency stability across the -20°C to 70°C commercial range is adequate for general-purpose serial links; a design targeting PCIe Gen4 or 5 with tighter ±25 ppm jitter budgets would need a different stability grade. The wide 2.25V to 3.6V supply rail lets this oscillator run from either a 2.5V or 3.3V rail — useful when the same BOM serves both voltage domains.
This is useful for power-sensitive designs where the reference clock can be gated during sleep modes — the 20 mA saving is modest but predictable.