100 MHz HCSL MEMS XO for PCIe clock trees
HCSL (High-Speed Current Steering Logic) delivers a 0.7 V swing into a 50-Ω termination to ground, which is the native input requirement for PCIe Gen1/2/3 PHYs and many FPGA SERDES blocks. Using an LVDS oscillator here would require an additional resistor network to shift the common mode.
MEMS resonator vs quartz — the reliability trade-off
Supply voltage spans 2.25V to 3.6V, so the same BOM line works across 2.5V and 3.3V rails without a separate regulator.