The LVDS output provides low-jitter differential signaling suitable for high-speed serial interfaces, FPGA reference clocks, and SerDes transceivers where single-ended CMOS would introduce common-mode noise.
6-SMD no-lead package and board integration
Housed in a 6-SMD no-lead package measuring 7.00 mm x 5.00 mm with a seated height of 0.90 mm, the DSC1123NI2-125.0000T fits a standard 7x5 mm oscillator footprint. The no-lead construction reduces parasitic inductance compared to a gull-wing lead frame, which helps maintain signal integrity at 125 MHz LVDS edge rates.
