LVDS output and supply tolerance — signal integrity across the board
LVDS differential output provides low-jitter, noise-immune clock distribution over long traces or cables, with a typical 100-ohm termination at the receiver — the 125 MHz rate suits SerDes, Ethernet PHY, or FPGA transceiver reference inputs. The 2.25V to 3.63V supply range lets this oscillator run from a 2.5V or 3.3V rail without an extra LDO, simplifying the power tree in mixed-voltage designs.
6-SMD no-lead package — footprint and layout fit
Housed in a 7.00 mm x 5.00 mm x 0.90 mm 6-SMD no-lead package, the DSC1123NI1-125.0000 is a surface-mount drop-in for standard 7x5 oscillator footprints — no special fan-out or via-in-pad required.