The LVDS output delivers a differential pair with low jitter and fast edge rates, making it a clean reference for automotive Ethernet, ADAS SoCs, or FPGA clock inputs that need a 100 MHz differential clock.
Supply rail and output compatibility
The supply voltage range spans 2.25V to 3.63V, covering both 2.5V and 3.3V rails without an external regulator. The LVDS output is AC-coupled into the receiver — the common-mode voltage is set by the receiver's internal bias, so the oscillator's 100 MHz differential pair mates directly with standard LVDS inputs on FPGAs or PHYs. The 6-SMD no-lead package measures 7.0mm x 5.0mm with a seated height of 0.9 mm.
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