212.5 MHz LVDS clock source with AEC-Q100 qualification
The DSC1123DL5-212.5000T: That stability band keeps the clock jitter within the link budget for 212.5 MHz serial protocols — the LVDS output pairs directly to a SerDes reference input without an external PLL clean-up. It is suited for engine-bay ECUs, ADAS camera modules, and infotainment head units where a commercial-grade XO would not survive the thermal cycling or vibration profile.
6-SMD package — board layout considerations
The 6-SMD, No Lead package measures 2.50 mm x 2.00 mm with a seated height of 0.90 mm. The supply voltage range is 2.25 V to 3.63 V, covering 2.5 V and 3.3 V logic rails without an external regulator. The LVDS output is AC-coupled internally — the receiver side must provide the common-mode bias; check the input termination in the downstream SerDes datasheet.