The DSC1123DL5-156.2500T delivers a 156.25 MHz LVDS output from a MEMS resonator, offering a drop-in replacement for quartz-based XOs in high-speed clock trees. The LVDS differential pair provides low jitter and common-mode rejection, making it suited for 1 Gigabit Ethernet PHY reference clocks, FPGA transceiver banks, and SerDes PLL references that require a 156.25 MHz input.
AEC-Q100 qualification and active production status
The OEM auditor will ask for PPAP documentation — this part supports that submission.
The 6-SMD, no-lead package measures 2.50 mm x 2.00 mm with a seated height of 0.90 mm max. The 0.098" x 0.079" footprint fits the standard 2.5 x 2.0 mm oscillator land pattern; the four corner pads are the signal and power connections, while the two centre pads are no-connect.