The LVDS output delivers the differential swing needed for high-speed clock distribution to FPGAs, SerDes transceivers, or Ethernet PHYs without the common-mode noise coupling that single-ended clocks pick up on long traces. The supply voltage accepts 2.25 V to 3.63 V, so it can run from a 3.3 V or 2.5 V rail directly.
AEC-Q100 qualification and MEMS shock tolerance
Housed in a 6-SMD no-lead package measuring 2.50 mm x 2.00 mm with a seated height of 0.90 mm max.
