125 MHz LVDS MEMS oscillator with AEC-Q100 grade
The DSC1123DL2-125.0000 is a MEMS-based XO (Standard) delivering a 125 MHz LVDS clock output from a 2.25V to 3.63V supply rail. The LVDS differential pair provides low-jitter clocking for high-speed SerDes, FPGA reference clocks, or Ethernet PHY interfaces — the 32 mA max supply current includes the output drive into a 100-ohm termination. AEC-Q100 qualification means this part passed the automotive-grade stress tests: temperature cycling, ESD, and latch-up.
Package and footprint for board layout
6-SMD, No Lead package measuring 2.50 mm x 2.00 mm with a seated height of 0.90 mm. The 0.50 mm pitch pads require a standard land pattern — no via-in-pad needed. The Enable/Disable function lets the system pull the output to high-Z for power savings; the disable current drops to 22 mA max.
Sourced through independent distribution; quoted to order against the BOM quantity.