125 MHz LVDS timing reference with MEMS reliability
The LVDS output delivers a low-jitter differential clock suitable for high-speed serial links, FPGA reference clocks, and networking PHYs. Supply voltage spans 2.25V to 3.63V, so the same part works on 2.5V or 3.3V rails without a separate LDO.
Industrial temperature grade and ±50 ppm stability
The 6-SMD no-lead package (2.50mm x 2.00mm footprint, 0.90mm seated height) is a standard MEMS oscillator footprint, compatible with automated pick-and-place and reflow assembly.