409.375 MHz LVDS clock with MEMS resonator
Output is LVDS, which gives a differential signal with typical 350 mV swing into a 100-ohm termination — the common-mode rejection rejects ground bounce and supply noise that a single-ended clock would couple into the data path.
Frequency stability and supply range
Supply voltage spans 2.25 V to 3.63 V, covering 2.5 V and 3.3 V rails with margin — no external LDO is needed when the rail is within that window, and the enable/disable function lets the system gate the clock without a separate load switch.
AEC-Q100 qualification and package
Packaged in a 6-SMD, No Lead ceramic-composite package measuring 3.20 mm x 2.50 mm with a seated height of 0.90 mm — the small footprint fits dense PCB layouts, but the 6-pad land pattern requires a soldering profile matched to the MEMS die's thermal mass for void-free reflow.
No stock-holding claim — quoted to order.