The wide supply range of 2.25V to 3.63V lets it run directly from a 2.5V or 3.3V rail without an extra LDO, simplifying the power tree.
LVDS output and enable/disable function for high-speed clock trees
LVDS differential output at 244 MHz provides the low-jitter, low-noise clock needed for SerDes, FPGA transceivers, or Ethernet PHY reference clocks.
6-SMD no-lead package – layout and footprint
Housed in a 6-SMD, no-lead package measuring 3.20 mm x 2.50 mm with a seated height of 0.90 mm max, the DSC1123CI2-244.0000 fits tight board layouts and reflows with standard SMT profiles. Surface-mount mounting — the no-lead package requires a solder-paste stencil with apertures matching the pad layout in the datasheet; no through-hole holes needed.
Suitable for both new design-ins and ongoing production.