The LVDS output swings 350 mV typical into a 100-Ω differential termination, keeping edge rates clean for SerDes, FPGA reference clocks, and Ethernet PHY interfaces without the common-mode noise coupling of single-ended clocks.
AEC-Q100 qualification and active lifecycle
No official successor or direct pin-compatible replacement is listed. For a BOM line already using this part, the DSC1123 series shares the same 6-SMD footprint across frequencies, so a frequency change (e.g., to 125 MHz or 200 MHz) keeps the same PCB layout.