125 MHz LVDS clock source — MEMS, not quartz
Output is LVDS, so the signal is a differential pair with typical 350 mV swing into a 100 Ω termination.
Supply voltage spans 2.25 V to 3.63 V, covering both 2.5 V and 3.3 V rails without an intermediate regulator. At 125 MHz LVDS, the 32 mA ceiling is the number to budget in a multi-oscillator design — four of these on a board add 128 mA to the 3.3 V rail, which is within the margin of a typical 500 mA LDO but worth checking against the regulator's rated output.
Temperature range and stability
That stability spec holds the output frequency within 50 ppm of 125 MHz across the full temperature band — tight enough for a 1 GbE reference clock (±100 ppm is typical for the PHY) without needing a TCXO.
6-SMD, no-lead package, 3.20 mm × 2.50 mm body, seated height 0.90 mm max. The 0.126" × 0.098" footprint is a standard 6-pad XO layout — no via-in-pad required, and it fits the same land pattern as many 3.2×2.5 mm LVDS oscillators from other vendors.
Product status is Active — Microchip continues to manufacture and support this order code.