125 MHz LVDS timing for industrial and networking boards
The DSC1123BL5-125.0000: LVDS signalling keeps the edge rates clean for 125 MHz clock distribution over short PCB traces — the differential pair reduces radiated EMI compared to a single-ended CMOS output at the same frequency.
A MEMS base resonator replaces the quartz crystal — no external load capacitors, no crystal start-up time, and better shock/vibration tolerance per the DSC1123 series design. The 6-SMD no-lead package (5.00 mm x 3.20 mm, 0.90 mm seated height) fits a standard oscillator footprint; the Enable/Disable function lets the system gate the clock for power savings without a separate clock buffer.