287 MHz LVDS clock for high-speed serial links
The DSC1123AM1-287.0000 delivers a 287 MHz LVDS output from a MEMS resonator — the frequency and signaling pair it for clocking a 10 GbE PHY, a SerDes reference, or an FPGA transceiver bank that expects LVDS on the input. LVDS differential swing keeps the edge rates clean across a short PCB trace; the 32 mA max supply draw is the total current budget for the oscillator itself, not counting the line termination.
Supply flexibility and frequency hold-in
The 2.25V–3.63V supply range lets this oscillator run off a 2.5V or 3.3V rail without a dedicated LDO — useful when the FPGA bank voltage is already set. The ±50 ppm absolute pull range is the total frequency variation over voltage, temperature, and aging; a system PLL that needs better than 50 ppm total drift must budget the oscillator's APR into its hold-in calculation.