322.2656 MHz LVDS clock for SERDES and FPGA reference
The DSC1123AI5-322.2656 is a MEMS-based XO (Standard) oscillator delivering a 322.2656 MHz LVDS output — a frequency commonly used as a reference clock for 10 Gigabit Ethernet PHYs, FPGA transceivers, and high-speed SERDES. The LVDS differential pair keeps jitter low over board traces longer than a few inches, which a single-ended CMOS clock at this frequency would struggle to maintain without signal degradation.
The supply range spans 2.25V to 3.63V — it runs from a 2.5V or 3.3V rail without a separate LDO.
