175 MHz LVDS clock source for high-speed signal chains
The LVDS swing keeps jitter low over the 7.0 mm × 5.0 mm 6-SMD footprint.
Supply voltage tolerance and power-down gating
The wide 2.25V to 3.63V supply range lets this oscillator run from a 2.5V or 3.3V rail without an intermediate LDO — one less component in the power tree. The Enable/Disable function gates the LVDS output without removing power — useful for sequencing multiple clock domains during system sleep or for suppressing the clock during board-level debug to isolate noise sources.