187.5 MHz LVDS clock with automotive-grade reliability
The DSC1123AI2-187.5000: The LVDS output provides low-jitter differential signaling suitable for high-speed data converters, FPGAs, and SerDes reference clocks — the 187.5 MHz rate aligns with common Ethernet and video pixel clock multiples.
Supply range and enable/disable function
Operates from a single 2.25V to 3.63V supply, covering 2.5V and 3.3V rails without an external regulator — the wide tolerance absorbs rail ripple from a switching converter.
Housed in a 6-SMD, No Lead Exposed Pad package measuring 7.00 mm x 5.00 mm with a seated height of 0.90 mm — a standard 7x5 mm oscillator footprint that matches many quartz XO layouts, simplifying drop-in replacement.