The LVDS signalling delivers the low-jitter, differential edge rates required for 200 MHz clock distribution in high-speed serial links — think PCIe Gen 2, Gigabit Ethernet, or automotive video interfaces.
Supply voltage spans 2.25V to 3.63V, covering both 2.5V and 3.3V rails without an intermediate regulator. For a 200 MHz clock, ±50 ppm translates to a ±10 kHz absolute frequency error — well within the capture range of most SERDES PLLs.
Package and board layout note
Housed in a 6-SMD, No Lead Exposed Pad package measuring 7.00 mm x 5.00 mm with a seated height of 0.90 mm.
