What the LVPECL output and ±10ppm stability mean for your clock tree
The DSC1122NL5-025.0006T is a MEMS-based XO delivering a 25.0006 MHz LVPECL differential output — the LVPECL swing (typically 800 mVpp) drives long PCB traces and terminated transmission lines with low jitter, making it a fit for high-speed SERDES reference clocks or FPGA clock inputs that require a differential signal. Frequency stability is ±10ppm across the -40°C~105°C industrial range — this holds the clock edge within 0.001% of nominal over temperature, which matters for Ethernet PHY timing or precision ADC sample clocks where ppm drift directly affects link margin or conversion accuracy.
Operates from 2.25V to 3.6V, covering the common 2.5V and 3.3V logic rails without an external regulator — the wide input range simplifies BOM consolidation when the same oscillator is used across multiple voltage domains.
This is a current-design-in part, not a last-time-buy or NRND item. The 6-SMD, no-lead package (7.00mm x 5.00mm, 0.90mm seated height) is a standard MEMS oscillator footprint shared with many Microchip and SiTime parts — PCB layout reuse across alternate sources is straightforward.