100 MHz LVPECL MEMS oscillator for industrial clock trees
The LVPECL signalling delivers the fast edge rates and low jitter needed for high-speed FPGA reference clocks, SERDES PLLs, and 10G Ethernet PHY timing, where a single-ended CMOS output would degrade signal integrity over a long trace.
Supply flexibility and frequency stability
The 2.25V to 3.6V supply range lets the oscillator run directly from a 2.5V or 3.3V rail without an intermediate LDO — one less regulator in the BOM for a tight power budget.
Package and footprint for high-speed layout
Housed in a 6-SMD, No Lead package measuring 2.50 mm x 2.00 mm with a seated height of 0.90 mm. The small footprint and LVPECL output require careful impedance-controlled routing — the differential pair should be 50-ohm single-ended, 100-ohm differential, with the trace length matched to within 5 mm to minimise skew.