100 MHz LVPECL MEMS oscillator for differential clock trees
The LVPECL output is the differential signalling choice for 100 MHz+ clock distribution into FPGA reference clocks, SERDES reference inputs, or high-speed ADC/DAC sample clocks.
Supply range and enable/disable for power sequencing
Runs from 2.25V to 3.6V — covers 2.5V and 3.3V rails without a separate regulator.
The MEMS base resonator is inherently more resistant to vibration and mechanical shock than a quartz blank, which matters in motor-drive or automotive auxiliary applications.
Suitable for design-in on new production builds and ongoing BOM replenishment.