156.2422 MHz LVPECL clock source for SERDES and FPGA reference
The DSC1122CI5-156.2422T is a MEMS-based XO delivering a 156.2422 MHz LVPECL output — a common reference frequency for 10G Ethernet, CPRI, and JESD204B clock trees. LVPECL swing provides the edge rate needed to drive differential inputs on high-speed SERDES without additional buffering.
Power rail flexibility and disable function
The enable/disable pin pulls the output to high-Z; max disable current is 22 mA vs 58 mA active, useful for power-gating unused SERDES lanes during sleep.
MEMS resonator — sourcing and reliability angle
MEMS resonators are fabricated on standard CMOS lines — no quartz crystal supply constraints, shorter lead times, and better immunity to shock and vibration than quartz oscillators.