Differential clock for 47.998 MHz — LVPECL output
The LVPECL standard delivers a low-jitter, complementary clock pair that drives 50-Ω terminated lines directly — common in 10GbE, FPGA reference clocks, and high-speed ADC/DAC sampling clocks where single-ended LVCMOS would introduce common-mode noise.
Supply-range tolerance and current budget
The supply voltage spans 2.25 V to 3.6 V, covering 2.5 V and 3.3 V rails without an external LDO.
