LVPECL is a differential signal that rejects common-mode noise better than single-ended CMOS or LVCMOS, making it the usual choice for high-speed serial links like 10 GbE, Fibre Channel, and PCIe reference clocks where jitter budget is tight. The ±25 ppm frequency stability keeps the clock edge within a quarter of a unit interval at 150.75 MHz, sufficient for most high-speed serial links without needing a VCXO.
That disable current is still higher than a CMOS-output oscillator, which matters if the clock is gated for power savings in a battery-powered design.
Package and footprint – 3.2 mm × 2.5 mm 6-SMD
The 6-SMD, No Lead package measures 3.20 mm × 2.50 mm with a seated height of 0.90 mm. The land pattern is standard for this footprint class.
Lifecycle – active, no end-of-life notice
Product status is Active.