150 MHz LVPECL MEMS oscillator for high-speed clock trees
LVPECL is the go-to signaling for low-jitter clock distribution in 10G Ethernet, FPGA reference clocks, and high-speed ADC/DAC sampling — the differential pair needs 50-ohm termination to Vcc - 2V, not a simple pull-up. Supply voltage spans 2.25V to 3.6V, so it runs directly off a 2.5V or 3.3V rail without an extra LDO. The wide tolerance also covers rail droop in a power-sequenced board — no need for a separate regulator just for the oscillator. That's tight enough for most serial links (PCIe Gen1/2, SATA, 1GbE) without external trim capacitors.
No last-time-buy scramble; you can quote it against a production BOM without obsolescence risk.
Termination and AC-coupling for LVPECL
LVPECL output requires a DC bias path — the 150 MHz signal must be terminated with 50 ohms to Vcc - 2V, or AC-coupled into a 100-ohm differential termination at the receiver. The DSC1122CI2-150.0000T's output driver is designed for that; a simple Thevenin equivalent (two resistors to Vcc and GND) works if a -2V rail isn't available.