148.5 MHz LVPECL MEMS oscillator for high-speed clock trees
LVPECL differential signalling at 148.5 MHz suits it for clocking high-speed ADCs, FPGAs, and SERDES interfaces where jitter budget and common-mode noise rejection matter.
Operates from a 2.25V to 3.6V supply rail, so it can run directly off a 2.5V or 3.3V rail without an intermediate LDO.
Housed in a 6-SMD no-lead package measuring 3.20 mm x 2.50 mm with a seated height of 0.90 mm — a compact footprint that fits tight channel spacing on a 10 GbE line card or FPGA mezzanine.
