MEMS oscillator at 133.33 MHz with LVPECL output
The DSC1122CI2-133.3300T: The LVPECL output provides the low-jitter, differential signalling needed for high-speed SERDES, FPGA reference clocks, and 10G Ethernet PHY timing — the 133.33 MHz frequency is a common multiple for 10GBASE-R and CPRI line rates.
Enable/disable function and supply current
An enable/disable pin lets the system hold the oscillator in a low-power state — supply current drops from 58 mA (max) when enabled to 22 mA (max) when disabled, useful for power-sensitive designs that gate the clock during sleep modes.
Housed in a 3.20 mm x 2.50 mm 6-SMD no-lead package, 0.90 mm seated height — the compact footprint suits dense PCB layouts where a quartz crystal plus oscillator IC would consume more board area. The MEMS resonator eliminates the quartz crystal's mechanical sensitivity to vibration and shock, making the DSC1122CI2-133.3300T a fit for industrial motor drives, outdoor telecom cabinets, and other environments where board-level vibration is a concern.
Sourced through independent distribution; quoted to order against the BOM quantity.