Frequency stability is ±25 ppm across the full temperature range, which keeps the 65 MHz clock within 1.6 kHz of nominal — sufficient for 1 GbE reference clocks and most FPGA transceiver PLLs.
Supply voltage tolerance and power budget
6-SMD no-lead package — board-fit note
The 3.20 mm x 2.50 mm x 0.90 mm 6-SMD no-lead package is a standard footprint — the 0.126" x 0.098" land pattern matches the common 3.2 x 2.5 mm oscillator pad layout. No via-in-pad required; the exposed centre pad (if present) should be connected to ground plane with a single via to avoid solder wicking.