400 MHz LVPECL clock source with MEMS reliability
Its LVPECL output delivers the fast edge rates and differential signalling needed for high-speed SerDes reference clocks, FPGA transceiver banks, and 10/25/40 GbE PHYs — the 400 MHz fundamental frequency means you avoid the phase-noise penalty of a PLL multiplier.
No forced last-time-buy or pin-compatible successor to track. The 6-SMD no-lead package (3.20 mm x 2.50 mm, 0.90 mm seated height) is a standard MEMS oscillator footprint, hand-solderable with a fine-tip iron and a steady hand — a weekend project board is feasible.