364 MHz LVPECL clock — what the output type means for your board
The DSC1122CE5-364.0000: This is a 364 MHz LVPECL oscillator — the differential output delivers a 800 mV typical swing into a 50-ohm terminated pair, which is the standard for high-speed SerDes reference clocks (PCIe Gen3/4, 10GbE, SFP+). The LVPECL logic family requires DC-termination to VCC – 2V; a simple Thevenin-equivalent resistor network at the receiver input sets the bias point. Do not route this as a single-ended signal — the common-mode rejection of the differential pair is what keeps the jitter below the link budget.
The supply range spans 2.25V to 3.6V, so the same part works on a 2.5V or 3.3V rail — no separate LDO needed. The LVPECL output swing scales with VCC; at 3.3V the differential swing is approximately 800 mV, at 2.5V it drops to about 600 mV. Confirm the receiver's input threshold and common-mode range at your chosen supply voltage.
Frequency stability and temperature grade
For a 364 MHz carrier, ±10 ppm translates to a maximum frequency deviation of ±3.64 kHz — well within the pull-in range of a typical SerDes CDR. The commercial temperature grade suits indoor equipment, networking gear, and test instrumentation; for outdoor or extended-temperature enclosures, a wider-range variant from the DSC1122 family would be needed.