200 MHz LVPECL MEMS oscillator for high-speed clock trees
The LVPECL differential output delivers the low-jitter clock needed for 10 GbE PHYs, FPGA transceivers, and high-speed SERDES links where a single-ended CMOS clock would introduce too much phase noise.
The supply range spans 2.25 V to 3.6 V, covering common 2.5 V and 3.3 V rails without an external regulator.
