MEMS-based 25 MHz LVPECL clock source
The LVPECL output delivers the fast edge rates and low jitter needed for high-speed clock distribution to FPGAs, SERDES, or Gigabit Ethernet PHYs. Supply voltage spans 2.25V to 3.6V, so it runs from a 2.5V or 3.3V rail without a separate LDO.
Housed in a 6-SMD, no-lead package measuring 5.00 mm x 3.20 mm with a seated height of 0.90 mm. The 0.50 mm pitch and no-lead construction mean the PCB footprint should match the recommended land pattern — no through-hole rework.
