375 MHz LVPECL clock for SERDES and FPGA transceivers
The DSC1122AI5-375.0000T: This is a 375 MHz MEMS-based oscillator with LVPECL output — the differential signaling and frequency target SERDES reference clocks, 10G Ethernet PHY, and FPGA high-speed transceiver banks where CMOS or LVDS fall short on edge rate or common-mode range.
