156.25 MHz LVPECL MEMS oscillator for high-speed clock trees
LVPECL signalling at this frequency suits high-speed serial links, FPGA reference clocks, and 10GbE PHY timing where the differential swing and fast edge rates keep jitter within the link budget.
Operates from a 2.25V to 3.6V supply rail, drawing 58mA max when enabled and 22mA max when disabled — the Enable/Disable pin lets the system gate the clock for power savings without removing the supply.
Housed in a 6-SMD, No Lead Exposed Pad package measuring 7.00mm x 5.00mm with a seated height of 0.90mm — the exposed pad requires a thermal via pattern under the package for proper solder-joint reliability and heat dissipation.