75 MHz LVPECL clock from a MEMS resonator
The DSC1122AE1-075.0000 is a MEMS-based XO (Standard) delivering a fixed 75 MHz LVPECL output — the LVPECL signal standard provides a differential, low-jitter clock with a typical swing of 800 mV p-p into a 50-Ω terminated line, which is the right drive for FPGA reference clocks and high-speed SerDes PLLs that need a clean edge rate and common-mode rejection.
Supply tolerance and temperature band
Frequency stability is ±50 ppm over the full temperature and supply range — that is tighter than a basic quartz XO (±100 ppm) and keeps the clock within one slot of a 100BASE-T Ethernet or PCIe Gen1 reference budget.
Enable/Disable and power control
The Enable/Disable function (pin 1) lets the system shut down the oscillator when the clock domain is idle — the disable current is 22 mA max versus 58 mA max active, saving 36 mA per clock tree branch in a power-sensitive design.