Frequency stability is held to ±25 ppm over that entire span, which keeps the clock within tight tolerance for UART bit rates, CAN bus, and MCU PLL references without external trim components.
Supply voltage flexibility and enable/disable function
It is a current design-in part. No stock-holding claim — quoted per order.
6-VDFN package — board layout note
Housed in a 6-VDFN package measuring 2.50 mm x 2.00 mm with a seated height of 0.90 mm — a compact footprint that fits under low-profile enclosures or alongside dense BGA clusters. No via-in-pad needed unless routing density forces it.