Frequency stability and temperature grade
The DSC1121BI1-008.0000T: For a 8 MHz clock, ±50 ppm translates to a maximum drift of ±400 Hz — well within the tolerance for most MCU and FPGA clock inputs, but worth checking if the downstream PLL has a narrow capture range. This footprint matches the standard 5x3.2 mm oscillator land pattern, so a board layout for a quartz XO of the same size accepts this MEMS part without a respin.
