Operating from 2.25V to 3.6V, the DSC1121AM2-040.0000 runs directly off a 2.5V or 3.3V rail without an intermediate LDO — the CMOS output swings rail-to-rail, so it drives standard 3.3V logic inputs cleanly. The 40 MHz output is a single-ended CMOS signal, compatible with most MCU clock inputs, Ethernet PHY reference clocks, and FPGA global clock buffers.
Housed in a 6-SMD, No Lead Exposed Pad package measuring 7.00mm x 5.00mm with a seated height of 0.90mm, the DSC1121AM2-040.0000 fits standard oscillator footprints and reflow profiles.
