The MEMS die is sealed in a 6-SMD no-lead exposed pad package measuring 7.00 mm x 5.00 mm, surface-mount compatible with standard reflow profiles. For a 50 MHz clock, ±10 ppm translates to ±500 Hz of absolute jitter budget — enough margin for a 100BASE-TX Ethernet PHY or a CAN-FD controller without external PLL cleanup.
Supply range and enable/disable function
Supply voltage spans 2.25 V to 3.6 V, covering 2.5 V and 3.3 V logic rails without an external regulator. The Enable/Disable pin (tri-level: high = output, low = high-Z, float = output) lets a system microcontroller gate the clock to a peripheral, saving 22 mA max in the disabled state against 35 mA max when running.